A Fault Tolerant Threshold Logic Gate Design
نویسندگان
چکیده
Threshold Logic gate is used as design abstraction for most nano devices and perceived as an alternate emerging technology to CMOS implementation. It is vulnerable to manufacturing inaccuracies that alter weight values which inadvertently affect the functionality of the gate. Hence fault tolerance should be taken in to consideration during the design of threshold logic gates to tolerate manufacturing defects to the maximum possible extent. In this work, a fault tolerant design methodology for threshold logic gate is presented.
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